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|Autori: ||Caruso, Enrico|
|Supervisore afferente all'Università: ||PALESTRI, PIERPAOLO|
|Centro di ricerca: ||DIPARTIMENTO POLITECNICO DI INGEGNERIA E ARCHITETTURA - DPIA|
|Titolo: ||Performance evaluation of III-V compound semiconductor n-MOSFETs employing calibrated multi-valley and Multi-Subband Monte Carlo transport models|
|Abstract (in inglese): ||For the last few decades, Si CMOS technology has been driven by device scaling to increase performance, as well as reduce cost and maintain low power consumption. However, as devices are scaled below the 100 nm region, performance gain has become increasingly difficult to obtain by traditional scaling. A paradigm shift has been occurring in the industry, where materials innovation, rather than scaling, is becoming the primary enabler for performance enhancement in CMOS technology.
To improve the drive current high electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability.
A realistic modeling approach of modern devices should be able to take into account the most relevant technological options to save development, implementation time and costs.
In this context, the aim of this PhD thesis is to calibrate and validate a state of the art Multi-Subband Monte Carlo (MSMC) simulator and employ it to investigate the performance of III-V nMOSFET.
We first validate the band structure calculation method used in the MSMC simulator, which is a key ingredient for accurate electrostatics and transport models. We cross check different band structure methods and provides useful parameter sets for an accurate description of III-V MOS band-structures in nanoscale Ultra Thin Body (UTB) MOSFET architectures, also in presence of strain. The scattering parameter of III-V semiconductor used in the models implemented in the MSMC simulator have been calibrated against experimental results: for phonon scattering we have used bulk velocity-field curves, while for surface roughness and Coulomb scattering we have used inversion layer mobility experiment.
Then, using the calibrated Multi-Subband Monte Carlo method we simulate the velocity-field of thin film III-V MOSFETs showing the effects of surface roughness scattering on the characteristics and provide useful curve to support the calibration of TCAD transport models for ultra-thin-films.
We evaluate the digital and analog figures of merit at two future technology nodes of ultra-scaled gate length taking into account all the main physical mechanism of the device, such as surface roughness, interface states and series resistances, understanding how these effects affect the MOSFET performance.
Strain engineering is an established technology booster for high-performance silicon MOSFETs. For III-V semiconductors, however, very little data on strain-induced performance improvement is available. For this reason, we analyze the effect of different strain configuration on an ideal III-V MOSFET, finding that none of them significantly improve the intrinsic performance of these devices.
Moreover, we have analyzed also the case of compressively strained (111) GaAs UTB MOSFET, which enable the transport in L-valleys providing a viable solution to the “DoS bottleneck”. Unfortunately, the results show that L-valley-enhanced transport most likely will not yield the Ion and switching time improvements observed in simple ballistic simulations, even if considering the ideal material properties and purely phonon scattering limited transport. In fact, the increased DoS and inversion charge at the virtual source provided by the L-valleys in the strained material is counterbalanced by an increased phonon scattering rate and reduced carrier velocity.
Finally, we extracted interface trap densities (Dit ) in the oxide/III-V gate stacks fitting multi-frequency C-V using TCAD simulations. In this way it is possible to overcome the measurement uncertainty and study also the dynamic properties of traps.|
|Parole chiave: ||III-V Semiconductor MOSFET; Strain; Traps; Multi-Subband Monte Carlo|
|MIUR : ||Settore ING-INF/01 - Elettronica|
|Corso di dottorato: ||Dottorato di ricerca in Ingegneria industriale e dell'informazione|
|Ciclo di dottorato: ||29|
|Università di conseguimento titolo: ||Università degli Studi di Udine|
|Luogo di discussione: ||Udine|
|Altre informazioni: ||Co-supervisori: Luca Selmi, David Esseni|
|Citazione: ||Caruso, E. Performance evaluation of III-V compound semiconductor n-MOSFETs employing calibrated multi-valley and Multi-Subband Monte Carlo transport models. (Doctoral Thesis, Università degli Studi di Udine, 2017).|
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